Error Correction Scheme for Constrained Inter-Cell Interference in Flash Memory

As NAND Flash memory process technology scales below 32nm and the number of charge levels per cell exceeds four, cell threshold voltage distributions must be narrower in order to prevent errors resulting from distribution overlap [3, 5, 6]. An obstacle to achieving narrow distributions is the floating-gate (FG) to floating-gate coupling [4, 6]. This coupling shifts the threshold voltages by a degree that depends on the level of coupling between adjacent cells and on the amount of charge in the surrounding cells. The effect manifests itself as an apparent broadening of the threshold voltage distributions.